The present invention relates to address detection circuits, and more particularly to an address detection circuit for use in communication systems having a plurality of communication nodes wherein communication is controlled on the basis of transmit/receive addresses included in packet signals and the like.
Whereas addresses are used in the reception or routing of packet signals, such processing as address detection and address calculation have conventionally been achieved with a computer. However, real time processing is difficult in this manner because the processing speed is not high enough. Meanwhile, there is proposed an address detection circuit using a memory which compares the addresses of packet signals with addresses stored therein to make real time processing possible. However, when a memory is used for address detection, the number of bits for address representation increases with the extension of the address length, and accordingly the memory capacity has to be increased. Since long addresses, such as 16-bit, 32-bit or even 48-bit ones, are used in local area networks or the like, the memory-based address detection circuit is hardly applicable for practical purposes.